Electronic Design Technologies, LLC
Introducing our up-coming Hardware/Software Language, Spectrum, and compiler that enable hardware and software engineers to create and innovate advanced digital systems. Providing for both high-level algorithmic abstraction level description as well as lower, RTL-like process level description to support the development of today's complex digital designs.
Revolutionizing Digital Design
Our Goals:
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Advance the rate and degree of world-wide technological progress by providing industry-leading hardware/software system design and development tools and complementary components.
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Provide end-to-end solutions which are first-in-class for FPGA, GPU, ASIC, HPC, AI, and embedded system development.
Spectrum - a Hardware/Software
Design Language
A more powerful "Hello, World!"
When people speak of "Hello, World!," they think of the software language standard for demonstrating the basic syntax of a language. However, in the realm of digital hardware and VHDL/Verilog HDL descriptions, "Hello, World!" has been reduced to a simple blinking LED. The example Spectrum code shown here is "Hello, World!" in Spectrum, but rather than flash an LED, this code sends the text of "Hello, World!" across a UART/USB connection from an FPGA board to a laptop for displaying in a terminal program. In this case, the text is printed on the terminal each second. This design uses a standard Clock domain (which is included automatically when not specified directly), a synchronizer for the start button on the FPGA board, a UARTSend module, a real-time timer for display the text in second intervals, and a Printer module with a method "Print" for displaying a generic string parameter. That string is converted at compile time to a byte array for the ROM using the meta-programming (compile-time execution) function "ToStringMem()." The "atl" block in the HelloWorldUART module is the algorithmic-transactional level behavior for the print loop. In the ROM1 Module, the "Read" method uses an FSM in a "tpl," transactional-process level, block to precisely specify the timing of the behavior for the ROM1 read.